1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art
There has been a semiconductor device manufacturing method including a process to form a via and an interconnect by forming an opening in an insulating layer formed on a substrate, and filling the opening with a metal such as copper.
By the semiconductor device manufacturing method, problems such as nonconductivity and high resistance might be caused when a metal fills the opening having foreign matter existing therein. Therefore, there is a demand for a means to prevent such problems.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-527691 discloses a semiconductor device manufacturing method that includes a first ashing process and a second ashing process as the process for removing a photoresist. The photoresist is formed immediately above a low-permittivity substrate layer such as a SiOC material after an opening is formed in the low-permittivity substrate layer. The first ashing process is to be performed after an opening is formed in a low-permittivity substrate layer such as a SiOC material formed on a substrate. The first ashing process is a process for removing the photoresist formed immediately above the low-permittivity substrate layer. The second ashing process is to be performed after the first ashing process is performed, and is to be performed under the condition that the chamber pressure is lower than 20 mTorr.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-527691 also discloses that, in the above described second ashing process, the density of oxygen-containing radical in a plasma environment becomes lower, and accordingly, detrimental oxidation of the dielectric substrate layer can be reduced (paragraph [0016] of Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-527691). Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-527691 also discloses that, through the second ashing process, the invasion of the cap layer serving as the bottom face of the opening can be minimized.
Therefore, according to the semiconductor device manufacturing method disclosed in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-527691, the second ashing process is performed for a period of time only long enough to remove the residuals after the ashing and the remaining photoresist.